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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH32S72BAFA is 33554432 - word x 72-bit Synchronous DRAM stacked structural module. This consist of thirty-six industry standard 16M x 4 Synchronous DRAMs in TSOP. The stacked structure of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.
85pin
1pin
FEATURES
Type name Max. Frequency CLK Access Time [latch mode] (CL = 4)
94pin 95pin
10pin 11pin
MH32S72BAFA-7 MH32S72BAFA-8
100MHz 100MHz
6ns 6ns
Back side
Front side
124pin 125pin
40pin 41pin
Utilizes industry standard 16M X 4 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package , and industry standard PLL in TSSOP package. Single 3.3V +/- 0.3V supply Burst length 1/2/4/8/Full Page (programmable) Burst type sequential / interleave (programmable) Column access random Burst Write / Single Write (programmable) Auto precharge / Auto bank precharge controlled by A10 Auto refresh and Self refresh LVTTL Interface 4096 refresh cycles every 64ms Intel specifiation(rev. 1.0)compliant PCB and SPD 1.2A
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin
84pin
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PIN NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE0 DQMB0 DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0
PIN NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
PIN NAME VSS NC /S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD
PIN NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 NC
PIN NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
PIN NAME VSS CKE0 /S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
NC = No Connection
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add CKE0 /S0-3 DQM0-7 /W /RAS /CAS REGE Vdd
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CB0 CB1 CB2 CB3 Registered Buffer
RCKE0 R/S0-3 RDQM0-7
D0
D18
D1
D19
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB4 CB5 CB6 CB7
D9
D27
D10
D28
D2
D20
D11
D29
D3
D21
D12
D30
D4
D22
D13
D31
D5
D23
D14
D32
D6
D24
D15
D33
D7
D25
D16
D34
D8
D26
D17
D35
From PLL
CK0 CK1 - CK3 RCKE0 R/S0 R/S1 R/S2 R/S3
PLL Terminated
D0-35 D0-3,D8-12,D17 D18-21,D26-30,D35 D4-7,D13-16 D22-25,D31-34
RDQM 0 RDQM 1 RDQM 2 RDQM 3 RDQM 4 RDQM 5 RDQM 6 RDQM 7
SERIAL PD SCL D0-1,D18-19 A0 A1 A2 WP D2-3,D8,D20-21,D26 47K SA0 SA1 SA2 D4-5,D22-23 D6-7,D24-25 VDD D9-10,D27-28 D11-12,D17,D29-30,D35 VSS D13-14,D31-32 D15-16,D33-34
SDA
D0 to D35 D0 to D35
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MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0 Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When /S is high,any command means No Operation. Combination of /RAS,/CAS,/W defines basic commands. A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-9.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA0,1 specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands
CKE0
Input
/S0 - 3 /RAS,/CAS,/W
Input Input
A0-11
Input
BA0-1 DQ0-63 CB0-7
Input
Data In and Data out are referenced to the rising edge of Input/Output CK Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
DQM0-7
Input
Vdd,Vss
Power Supply Power Supply for the memory mounted module. Register enable:When REGE is low,All control signals and address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode)
REGE
Output
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH32S72BAFA provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK /S /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with AutoPrecharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS /CAS X H L L L H X H H H H L /WE X H H L L L BA0,1 X X V V X V A11 X X V X X X A10 X X V L H L A0-9 X X V X X V
WRITEA
H
X
L
H
L
L
V
X
H
V
READ
H
X
L
H
L
H
V
X
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
X X X X X X L
H X X X X X L
V X X X X X V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS /CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L L L L L H L L L L L H H L L L H L H L BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 ACT PRE/PREA REFA MRS Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /S H L L L /RAS /CAS X X H H H H H L /WE Address X X HX L BA H BA,CA,A10 Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, WRITE/ Begin Write,Determine AutoWRITEA Precharge*3 ACT Bank Active/ILLEGAL*2 PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL Command DESEL NOP TBST
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
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MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State SELF REFRESH*1 CK n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CK n X H H H H H L X H L H L L L L L L X H L H L /S X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend Action
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command.
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE BA0,1 A11-A0
V
BA0 BA1 A11 A10 A9 0 0 0 0
A8
A7 A6 0
A5
A4 A3 BT
A2
A1 A0 BL
WM 0
LTMODE
LATENCY MODE
CL 000 001 010 011 100 101 110 111 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT
BL 000 001 010 011 100 101 110 111
BT= 0 1 2 4 8 R R R FP
BT= 1 1 2 4 8 R R R R
BURST LENGTH
WRITE MODE
BURST TYPE
0 SEQUENTIAL INTERLEAVED 1 R: Reserved for Future Use FP: Full Page 29.July.1998
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 39 0 ~ 70 -45 ~ 100 Unit V V V mA W C C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted) Symbol Vdd Vss VIH VIL Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 2.0 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vdd+0.3 0.8 Unit V V V V
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CK0 pin Input Capacitance, I/O pin Test Condition VI = Vss f=1MHz Vi=25mVrms Limits(max.) 20 20 20 29 Unit pF pF pF pF
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MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Parameter
operating current one bank active (discrete)
Symbol Icc1 Icc2P
Test Condition tRC=min.tCLK=min, BL=1, IOL=min
Limits (max) -7, -8 2411 107
Unit mA
precharge stanby current in power-down mode precharge stanby current in non power-down mode active stanby current in power-down mode active stanby current in non power-down mode
one bank active (discrete)
CKE=VILmax,tCLK=15ns Icc2PS CKE=CLK=VILmax(fixed) Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note) Icc2NS CKE=VIHmin,CLK=VILmax(fixed) Icc3P CKE=VILmax,tCLK=15ns Icc3PS CKE=CLK=VILmax(fixed) Icc3N CKE=/CS=VIHmin,tCLK=15ns Icc3NS CKE=VIHmin,CLK=VILmax(fixed) Icc4 tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte) tRC=min, tCLK=min Icc5 Icc6 CKE <0.2V
mA 71 mA 827 mA 755 mA 107 mA 71 mA 2015 mA 1475 mA 2501 5435 71 mA mA mA
burst current auto-refresh current self-refresh current
Note:Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC IOZ ) VOL(AC) Ii Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current High-Level Output Voltage(AC) Input Current Low-Level Output Voltage(AC) Test Condition IOH=-2mA IOL=2mA Q floating CL=50pF, VO=0 ~ Vdd IOH=-2mAIOL=2mA VIH=0 ~ Vdd+0.3V CL=50pF, Limits Unit Min. Max. 2.4 V 0.4 V -10 2 10 uA V 0.8 uA -10 10 V
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MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V LATCH MODE Limits Symbol Parameter Min. tCLK tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF CK cycle time CL=3 CL=4
10 10 3 3 1 2 0 70 20 50 20 10 20 10 20 10
-7 Max. Min.
13 10 4 4 1 2 0 70 20 50 20 10 20 10 20 10
-8 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Col to Col Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh Interval time
10
10
100000
100000
64
64
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter.
CK
1.4V
Any AC timing is referenced to the input signal crossing through 1.4V.
Signal
1.4V
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
16
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE Limits Symbol Parameter Min. tCLK tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF CK cycle time CL=2 CL=3
10 10 3 3 1 7 0 70 20 50 20 10 20 10 20 10
-7 Max. Min.
13 10 4 4 1 7 0 70 20 50 20 10 20 10 20 10
-8 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Col to Col Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh Interval time
10
10
100000
100000
64
64
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter.
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) LATCH MODE Limits Symbol Parameter Min. tAC tOH tOLZ tOHZ Access time from CK Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK CL=3 CL=4 3 0 3 6 -7 Max.
6 6
-8 Min. Max.
7 6
Unit
ns ns ns
3 0 3 6
ns
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
17
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE Limits Symbol Parameter Min. tAC tOH tOLZ tOHZ Access time from CK Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK CL=2 CL=3 3 0 3 6 -7 Max.
6 6
-8 Min. Max.
7 6
Unit
ns ns ns
3 0 3 6
ns
Output Load Condition
VTT=1.4V 50 DQ VOUT 50pF Output Timing Measurement Reference Point 1.4V CK 1.4V
CK
1.4V
DQ
tAC tOH
tOHZ
1.4V
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
18
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE DQM A0-9 A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 REGE DQ
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
19
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
tRAS
tRP tRCD
/RAS
tRCD
/CAS /WE
tWR tWR
CKE DQM A0-9 A10 A11
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
BA0,1
0
1
0
1
0
0
1
2
0
REGE DQ
ACT#0
D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 D0 D0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
20
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Lacth mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE DQM A0-9 A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 REGE
0
0
0
0
0
DQ
ACT#0
D0
D0
D0
D0
D0
D0
D0
D0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case 29.July.1998
MIT-DS-0243-0.0
MITSUBISHI ELECTRIC
21
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
tRAS
tRP tRCD
/RAS
tRCD
/CAS /WE
tWR tWR
CKE DQM A0-9 A10 A11
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
BA0,1 REGE
0
1
0
1
0
0
1
2
0
DQ
ACT#0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
22
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9
BL=4,CL=3,Buffer mode(REGE="L")
10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-9 A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 REGE
0
0
0
0
0
CL=3
DQ
ACT#0 READ#0
Q0
Q0
Q0
Q0
Q0
Q0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
23
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,CL=3,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRAS tRP tRCD tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-9 A10 A11 BA0,1
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
REGE
CL=3 CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0
DQ
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
24
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4, CL=3,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency =3
A0-9 A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 REGE
0
0
0
0
0
CL=3
DQ
ACT#0 READ#0
Q0
Q0
Q0
Q0
Q0
Q0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
25
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9
BL=4,CL=3,Latch mode(REGE="H")
10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRAS tRP tRCD tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency =3
A0-9 A10 A11 BA0,1
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
REGE
CL=3 CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0
DQ
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
26
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1
0
1
0
1
0
0
1
1
REGE
DQ
ACT#0 ACT#1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
27
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1
0
1
0
1
0
0
1
1
REGE
DQ
ACT#0 ACT#1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
28
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 REGE
0
1
0
1
0
0
1
1
CL=3
CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
DQ
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
29
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS /WE CKE DQM
DQM read latency =3
A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 REGE
0
1
0
1
0
0
1
1
CL=3
CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
DQ
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
30
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE DQ
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
31
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE DQ
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
32
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
1
0
CL=3
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
DQ
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
33
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
1
0
CL=3
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
DQ
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
0
1
0
CL=3
DQ
D0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
35
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
0
1
0
CL=3
DQ
D0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ REGE
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
37
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ REGE
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
39
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
tRSC
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
M
X
Y
X
X
BA0,1 DQ REGE
0
0
0
D0
D0
D0
D0
Auto-Ref (last of 8 cycles)
Mode Register Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
/RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
Y
X
X
BA0,1 DQ REGE
0
0
D0
D0
D0
D0
Auto-Refresh Before Auto-Refresh, all banks must be idle state.
ACT#0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped tRC
/CS /RAS /CAS /WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM A0-9 A10 A11 BA0,1 DQ REGE
X
X
X
0
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state.
Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state.
ACT#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
45
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
46
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9 A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
47
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM read latency=2
DQM A0-9 A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
48
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM read latency=3
DQM A0-9 A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
49
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS /CAS /WE
Standby Power Down
CKE
CKE latency=1
Active Power Down
DQM A0-9 A10 A11
X
X
X
BA0,1 DQ REGE
0
Precharge All
ACT#0
Italic parameter indicates minimum case MIT-DS-0243-0.0 29.July.1998
MITSUBISHI ELECTRIC
50
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
CKE latency=1 CKE latency=1
DQM A0-9 A10 A11
X
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 READ#0 CLK suspended
CLK suspended Italic parameter indicates minimum case 29.July.1998
MIT-DS-0243-0.0
MITSUBISHI ELECTRIC
51
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
CKE latency=1 CKE latency=1
DQM A0-9 A10 A11
X
Y
Y
X
X
BA0,1 DQ REGE
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 READ#0 CLK suspended
CLK suspended Italic parameter indicates minimum case 29.July.1998
MIT-DS-0243-0.0
MITSUBISHI ELECTRIC
52
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35 3
11.43
6.35 36.83 24.495 42.18
6.35 54.61 127.35
1.27
3
3 43.18 6.5 Max 6.88Min
29.July.1998
8.89
MIT-DS-0243-0.0
17.78 53
MITSUBISHI ELECTRIC
4
MITSUBISHI LSIs
MH32S72BAFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-0243-0.0
29.July.1998
MITSUBISHI ELECTRIC
54

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